Conventionally, a flash memory has typically been used as a nonvolatile semiconductor storage device.
In this flash memory, as shown in FIG. 23, a floating gate 902, an insulation film 907 and a word line (control gate) 903 are formed in this order via a gate insulation film 908 on a semiconductor substrate 901, and a source line 904 and a bit line 905 are formed on both sides of the floating gate 902, constituting a memory cell. Around this memory cell are formed element isolation regions 906 (refer to JP 5-304277 A).
The memory cell retains storage as the quantity of charge in the floating gate 902. In the memory cell array constructed by arranging the memory cells, the desired memory cell can be subjected to rewrite and read operations by selecting the specified word line and bit line and applying a prescribed voltage to the lines.
The flash memory as described above exhibits a drain current Id to gate voltage Vg characteristic indicated by the solid line curve and the dashed line curve in FIG. 24 when the quantity of charges in the floating gate 902 changes. That is, if the quantity of negative charges in the floating gate 902 is increased, then the characteristic curve changes from the characteristic indicated by the solid line curve to the characteristic indicated by the broken line curve in FIG. 29, and the Id-Vg curve is displaced roughly parallel in a direction in which the gate voltage Vg increases with respect to same drain current Id, and the threshold voltage increases.
However, in semiconductor storage devices of the prior art, since a high voltage is used in specific operations performed on memory elements, it is required to use thick gate insulation film of transistors in the memory elements as well as peripheral circuits. In consideration of the short-channel effect, therefore, it is also difficult to use transistors of relatively short gate length in the conventional transistors for the memory elements and the peripheral circuits. As a result, these cause a problem that areas of the memory cell array and peripheral circuits used at high voltages become large. Therefore, it is difficult to downsize the whole semiconductor storage devices.